Integrated circuits have used films of silicon dioxide and silicon nitride as insulating or dielectric layers to electrically isolate independent circuit components. Typical isolation schemes use dielectric isolation whereby trenches in a substrate layer are formed for receiving electrically isolating materials (oxides, polysilicon, etc.). After processing, the trenches electrically separate the microelectronic components constructed on either side of the isolation trench. The present invention is an improved method for isolation trench construction.
Microelectronic circuits, in the form of integrated circuits, are constructed in a multitude of process steps. Among the most crucial steps are the patterning process steps by which circuit patterns are permanently transferred onto the surface layers of semiconductor wafers. In order to accurately transfer a pattern, the wafer surface must be planar.
Wafer surface flatness is a critical requirement for small dimension patterning. A key element of patterning involves the projection of patterns onto the wafer's surface. This extremely delicate process involves the excruciatingly precise projection of the required patterns onto the wafer's surface in a uniform manner. If the surface is not flat, the projected image will be distorted, just as film images are out of focus on a non-flat screen. These distortions cause a number of undesirable effects. Wafer surface variation causes depth of field problems which cannot always be rectified, leading to increased incidence of wafer failure. Furthermore, as the wafer's circuits are layered upon one another, surface planarity defects are magnified. This effect greatly reduces process yield and is therefore highly undesirable.
Planarization of the wafer's surface is generally accomplished through CMP. CMP is effective in solving many surface uniformity problems. Unfortunately, prior art CMP techniques require many steps, are time consuming, and do not entirely solve the problem of surface uniformity.
The present invention solves many of these problems. The method eliminates excess masking and etching steps from the isolation trench formation process. The prior art dishing problems present in wide trenches are substantially reduced by the present invention. In short, the present invention improves efficiency, reduces manufacturing costs, simplifies manufacture, and reduces the overall process time. Critically, the invention achieves a more planar surface, and reduces significantly the dishing problems present in wide trenches that are common to all prior art CMP methods. The overall effect of the present invention is greater efficiency at reduced cost.
The Applicant's invention is most easily understood in view of the process techniques which currently exist in the art (FIG. 1). Prior art processes begin with ordinary silicon crystal wafers (which may be doped or not) (101). These are thermally oxidized to create a silicon dioxide layer (102), approximately 200-400 .ANG. deep ("d"). A layer of nitride is then deposited on the wafer in a thickness of between about 1,000-about 2,000 .ANG. (103). Commonly the layer of silicon nitride (Si.sub.3 N.sub.4) is approximately 1,700 .ANG. deep (103). This is the basic starting wafer.
The wafer is then masked with photoresist pattern (201) as shown in FIG. 2. A first etch is used to remove the nitride and oxide layers down to the silicon wafer surface, as in FIG. 3. A second etch step is used to remove the silicon surface area through the openings in the mask, creating trenches (301) as shown in FIG. 4.
FIG. 5 shows the silicon dioxide deposition layer (501) on the etched wafer of FIG. 4. Typical deposition is done using PETEOS or LPCVD techniques, but may be accomplished by any other silicon dioxide deposition methods. The wafer is then reverse masked with photoresist (601) as shown in FIG. 6. The wafer is etched a third time, leaving an irregular oxide profile (501A) after the photoresist is removed, as shown in FIG. 7. CMP is then used to grind and planarize the surface. The grinding continues until the surface is at least 100 .ANG. into the nitride layer, as shown in FIG. 8. This causes the depressions present in the trenches (8a, 8b, 8c). The effects are particularly pronounced in wide trenches (8c). A slight bowing of the pads used in the CMP process causes the lower surface areas (i.e. the isolation trenches) to be unintentionally ground down. This phenomenon is known as "dishing," and is undesirable for the reasons set forth above.